| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_7fd2448a658c5078bf1b9155c0e2d462 |
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28525
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1066
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-761
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-808
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823878
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-337
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8236
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-44 |
| filingDate |
2008-04-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_95208443762c449794c84a2a048eb553 |
| publicationDate |
2008-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2008272408-A1 |
| titleOfInvention |
Active area junction isolation structure and junction isolated transistors including igfet, jfet and mos transistors and method for making |
| abstract |
Integrated active area isolation structure for transistor to replace larger and more expensive Shallow Trench Isolation or field oxide to isolate transistors. Multiple well implant is formed with PN junctions between wells and with surface contacts to substrate and wells so bias voltages applied to reverse bias PN junctions to isolate active areas. Insulating layer is formed on top surface of substrate and interconnect channels are etched in insulating layer which do not go down to the semiconductor substrate. Contact openings for surface contacts to wells and substrate are etched in insulating layer down to semiconductor layer. Doped silicon or metal is formed in contact openings for surface contacts and to form interconnects in channels. Silicide may be formed on top of polycrystalline silicon contacts and interconnect lines to lower resistivity. Any JFET or MOS transistor may be integrated into the resulting junction isolated active area. |
| isCitedBy |
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| priorityDate |
2007-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |