| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b9aeecf9c02cfb75a2215d459406bd1f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0f0644bd217db97d9f5dc2f51a660eee
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6f8d44b8d5a824eb63b25f97bb3a488c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_7015c91aa68df785806a270c14c79bef
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3941ce382e3b5be546c41ac9e518afc1 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4975
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82345
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28097 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
| filingDate |
2007-03-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6e1acf8d7c62a1618b4fa88d6b260c69
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_707e4b6f72236ad7325b5c49f827701f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c907ee1928b548c0746ca13cd3c530ed
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e828356754b4ccdddbdec66c14a8a3c9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_20c1ed016739667926c48225d733ea6d |
| publicationDate |
2008-10-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2008237750-A1 |
| titleOfInvention |
Silicided metal gate for multi-threshold voltage configuration |
| abstract |
A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8330235-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011294287-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2009090977-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010314698-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011198670-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7749822-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2008164529-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8791528-B2 |
| priorityDate |
2007-03-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |