http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2008144243-A1

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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H02H9-04
filingDate 2007-05-14-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9fd99396f3c194f26aeca95c263657fa
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publicationDate 2008-06-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2008144243-A1
titleOfInvention Method and circuit for low-power detection of solder-joint network failures in digital electronic packages
abstract A low power circuit and method for detects in-situ failures or precursors to failures in solder-joint networks on actual operational devices and packages in the field. An amplifying detector such as provided by a common-gate transistor sources current to the network to generate a signal voltage and a reference voltage that is sensitive to the low voltage applied to the other side of the network. Generation of this self-adjusting reference voltage makes the detection circuit insensitive to the network low-voltage. Additional power savings and performance gains can be provided with the addition of a differential amplifier to set a fixed bias point and a level shifter to cancel noise. The detected failure or precursor of a selected monitor solder-joint network(s) is an indicator of the integrity of other operational solder-joint networks in the package, on the PWB or between PWBs.
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