| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6375082acaf7f919e9925e70b644d234 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-92244
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15787
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-19015
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-19105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-04105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-09701
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-1301
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73267
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32245
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32225 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-19
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-12 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-00 |
| filingDate |
2006-11-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5ce947e6f69aaede1a3ee75905d4f8ae
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_54144fd9a3cfe21a6a951236e7338cc3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0021ce365200c20f339a780fe9ffb69b |
| publicationDate |
2008-05-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2008122074-A1 |
| titleOfInvention |
Multi-chip electronic circuit module and a method of manufacturing |
| abstract |
An integrated circuit module has a substrate with an exposed surface. An integrated circuit die has a first surface and a second surface opposite the first surface, and has a plurality of bonding pads on the second surface. The integrated circuit die is positioned with its first surface on the exposed surface of the substrate. A plurality of dielectric layers cover the second surface of the integrated circuit die. At least one conductive layer is sandwiched between a pair of the plurality of dielectric layers, and forms one or more passive elements electrically connected to the plurality of bonding pads of the integrated circuit die, through one or more holes in one of the plurality of dielectric layers. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8564552-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011095996-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8970536-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2008238568-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7626472-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8773866-B2 |
| priorityDate |
2006-11-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |