| abstract |
The structure of the present invention comprises a semiconductor substrate and a trench region formed on the semiconductor substrate. The trench region includes an extended funnel portion in the vicinity of the semiconductor substrate surface. A device isolation layer is formed at the trench region. The device isolation layer includes a void formed at a lower level than the funnel portion. The sidewalls of the hard mask pattern and the internal walls of the trench region are etched to form a funnel portion with an extended trench region at the vicinity of the semiconductor substrate surface. Accordingly, the void in the trench region does not extend above a surface of the semiconductor substrate. |