| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28114
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66825
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40114
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-788 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
2006-02-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ad823d6a8699d89b5143b2b43fba5a19 |
| publicationDate |
2007-08-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2007202646-A1 |
| titleOfInvention |
Method for forming a flash memory floating gate |
| abstract |
A flash memory cell with an improved floating gate electrode and method for forming the same, the method including providing a semiconductor substrate active area electrically isolated by STI structures; forming a gate dielectric over the semiconductors substrate; forming a nitride mask layer on the gate dielectric and forming an opening in the nitride mask layer defining a floating gate electrode; backfilling the opening with polysilicon to form the floating gate electrode; and, isotropically etching the upper portion of the floating gate electrode to form a recessed area. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2008265302-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007296016-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7598562-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7576381-B2 |
| priorityDate |
2006-02-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |