| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318561
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318558
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318555
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318563
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-3177
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318572 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-3185
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28 |
| filingDate |
2007-01-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a80d6a9d8c490ac9f2fe550425bf7876 |
| publicationDate |
2007-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2007118780-A1 |
| titleOfInvention |
Hierarchical access of test access ports in embedded core integrated circuits |
| abstract |
An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9465073-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2015067425-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2008256405-A1 |
| priorityDate |
1998-02-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |