http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007103183-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_43e9bc481473b7735d51aacc3e34fbba |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-31917 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2889 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03H11-265 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03H11-126 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-13 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R1-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R- http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03H11-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03H11-12 |
| filingDate | 2006-12-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dd1c9b6297274c3e7cb8f6ddf1039ec7 |
| publicationDate | 2007-05-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-2007103183-A1 |
| titleOfInvention | Isolation Buffers With Controlled Equal Time Delays |
| abstract | A system is provided for controlling the delay in an isolation buffer. Multiple such isolation buffers are used to connect a single signal channel to multiple lines and controlled to provide an equal delay. Isolation buffer delay is controlled to be uniform by varying either power supply voltage or current. A single delay control circuit forming a delay-lock loop supplies the delay control signal to each buffer to assure the uniform delay. Since controlling delay can also vary the output voltage of each isolation buffer, in one embodiment buffers are made from two series inverters: one with a variable delay, and the second without a variable delay providing a fixed output voltage swing. To reduce circuitry needed, in one embodiment an isolation buffer with a variable power supply is provided in a channel prior to a branch, while buffers having a fixed delay are provided in each branch. A wafer test system can be configured using the isolation buffers having equal delays to enable concurrently connecting one tester channel to multiple wafer test probes. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7394301-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005231259-A1 |
| priorityDate | 2003-10-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 30.