http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007028146-A1

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_43dcdc768b0a1efa095f9d1f8bbbf789
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4078
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L1-00
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filingDate 2006-07-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_59a7e71330154259722072b7f24901f3
publicationDate 2007-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2007028146-A1
titleOfInvention Semiconductor memory device system, and method for operating a semiconductor memory device system
abstract A method for operating a semiconductor memory device system, and a semiconductor memory device system are disclosed. In one embodiment, the system includes a memory device and a control means connected with the memory device via a bus system, wherein a single signal line or a single signal line pair of the bus system is provided for the transmission of a status signal that signalizes that control data are to be transmitted from the memory device to the control means, or from the control means to the memory device.
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2020101975-A1
priorityDate 2005-07-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 38.