| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d4d2f6f4dae1e9e8623466d90f1cfedc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8de42e629231a36fec5161df86210448
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_24abc632452a3e762da94f73b41eefa4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a2b89f973867f67bb52fb62c3ee56ceb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_12c0ee25178e6e3aab044cb6a5edb665 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-324
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-321
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B99-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28052
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02274
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-42
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823443
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 |
| filingDate |
2006-06-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_977afc4d4516832f661ff1437b06569f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bc42ade3a6175d8810aef638472316b1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_08d58b078819634b20b1e3e571450be9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4d7479c7ff73fe7a9f85f7221a08c597
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_94e4de71f054d925a475c688571d7c8d |
| publicationDate |
2006-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2006292784-A1 |
| titleOfInvention |
Methods of Forming Integrated Circuit Devices Including Memory Cell Gates and High Voltage Transistor Gates Using Plasma Re-Oxidation |
| abstract |
A method of forming an integrated circuit device can include forming a plurality of stacked cell gates in a memory cell region of a semiconductor substrate and a plurality of high-voltage transistor gates in a peripheral circuit region of the semiconductor substrate. The semiconductor substrate including both the plurality of stacked cell gates and the plurality of high-voltage transistor gates is annealed and the annealed semiconductor substrate including both the plurality of stacked cell gates and the plurality of high-voltage transistor gates is plasma oxidized. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2009256211-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2009311877-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8993458-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8319341-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010283096-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8847300-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7932564-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7834387-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9514968-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2009008716-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010297854-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011042760-A1 |
| priorityDate |
2005-06-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |