Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3a90493d0ee1c33ea082f55256e2ee6d http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1f6149ef56bd997a1467e2c476cd867c http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_7df52f1a848032efc7d51959d4fcd2c9 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0bbdd75927fb9dd21cb5f68b2a8a03d6 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b6da7d1c8d9107ac5b8a551baf4704a5 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2855 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15311 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2856 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2853 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2879 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2875 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26 |
filingDate |
2006-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f72024a7625480b97aae44f5e14407b6 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3950f81e3d10c5745a27a4baae605292 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7bc59c11481cea73a40bd5b7aa5bc1a0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c9f4c3adb22988ebc7fb53a3ab58d2e8 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0f9642278e28af1439dba5cf55d8e574 |
publicationDate |
2006-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-2006290372-A1 |
titleOfInvention |
Packaging reliability super chips |
abstract |
A test chip module for testing the integrity of the flip chip solder ball interconnections between chip and substrate. The interconnections are thermally stressed through an array of individual heaters formed in a layer of chip metallurgy to provide a uniform and ubiquitous source of heat. Current is passed through the interconnection to be tested by a current supply circuit using one signal I/O interconnection and the voltage drop across the interconnection to be tested from the current passed therethrough is measured by a voltage measuring circuit connected through another signal I/O interconnection. Stress initiating cracking and degradation at the interconnection creates a measurable change in voltage drop across the interconnection. |
priorityDate |
2005-06-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |