| abstract |
A semiconductor memory device includes a serial to parallel converter configured to generate parallel data at a parallel data rate in response to first serial data at first serial data rate in a first mode and configured to generate the parallel data at the parallel data rate in response to a second serial data at second serial data rate in a second mode, wherein the second serial data rate is less than the first serial data rate, and a data write circuit configured to provide the parallel data to a memory cell array. |