| abstract |
A memory device includes a memory cell, a reference structure, and a sensing device. The memory cell includes an MR element and a pass transistor. The pass transistor, reference structure, and sensing device are connected to an input node. The logic state of the memory cell can be detected by a read operation that includes the sensing device sensing the voltage at the input node. The voltage at the input node will vary depending on the state of the MR element. The reference structure provides a voltage drop allowing for an increased read voltage to the memory cell. This in turn can provide for decreased read times. In some embodiments, the MR element can include a magnetic tunneling junction sandwiched between electrode layers. One of the electrode layers can be connected to a bit line, the other can be connected to the pass transistor. |