Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b2a8248c22a0d87fca1fbcafc080d1e2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9cafc86c4919952e1ec4717e7bb253b0 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-05 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-15 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05573 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05571 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-68345 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-68377 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-145 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-19041 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-09701 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15311 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-056 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73204 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-6835 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49816 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49822 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-4857 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49833 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-498 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-739 |
filingDate |
2006-05-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5b54cde53dc68b246835db47fab9d70f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c44c33798befb3d105697d10dd4550b6 |
publicationDate |
2006-10-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-2006231863-A1 |
titleOfInvention |
Manufacturing process of a chip package structure |
abstract |
A manufacturing process of a chip package structure is provided. The manufacturing method uses fine pitch circuit processes, such as a TFT-LCD process or an IC process, to increase layout density and shorten electrical transmission pathways so that a higher electrical performance level is attained. First, a multi-layered interconnection structure with high-density bonding pads and fine pitch circuit is formed over a hard support base plate having a large area and high degree of planarity. A die is attached to a top surface of the multi-layered interconnection structure. A plurality of opening is formed on a bottom surface of the support base plate. Contacts are positioned into the openings in the support base plate such that the contacts are electrically connected to an inner circuit within the multi-layered interconnection structure. |
priorityDate |
2003-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |