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filingDate 2006-03-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fd8c610e61a6899518bf7bc474a91f3b
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publicationDate 2006-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2006160353-A1
titleOfInvention Methods for selective integration of airgaps and devices made by such methods
abstract Damascene stacks for use in semiconductor devices and methods for making such stacks are disclosed. An example damascene stack includes a substantially planar lower liner layer and a patterned sacrificial dielectric layer disposed on top of the lower liner layer, where the patterned sacrificial dielectric layer includes an interconnect structure of the damascene stack. The example damascene stack further includes a substantially planar upper liner layer disposed on top of the patterned sacrificial dielectric layer, where the upper liner layer being formed of a material that is resistant to etching by a first etch compound. There is at least one plug-hole in the upper liner layer, where the at least one plug-hole is (i) adjacent to the interconnect structure and (ii) formed by locally converting a portion of the upper liner layer to be etchable by the first etch compound and removing the locally converted portion of the upper liner layer using the first etch compound. The example damascene stack still further includes at least one air gap formed by removing at least a portion of the sacrificial dielectric layer through the at least one plug-hole in said upper liner layer.
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