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filingDate 2004-11-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4a7b7f842f50edb4de878c60ba341df6
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publicationDate 2006-05-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2006110901-A1
titleOfInvention Minimizing resist poisoning in the manufacture of semiconductor devices
abstract The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via ( 160 ) in a substrate ( 130 ) and then forming a base getter material ( 210 ) in the via ( 160 ). The method further includes forming a photoresist layer ( 410 ) over the base getter material ( 210 ), the photoresist layer ( 410 ) having an opening ( 420 ) therein positioned over the via ( 160 ), and etching a trench ( 510 ) into the substrate ( 130 ) using the opening ( 420 ) in the photoresist layer ( 410 ).
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