| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_7a37d7a7385924dd55e29ac1e96d1492 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K1-0393
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2203-0307
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2203-0392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-28 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-382
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-244 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K1-00 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01B13-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K1-09 |
| filingDate |
2005-05-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e56b25466675e77ba31d1378706b6534
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6875e2d47227f52986fe5d3746ab2c82 |
| publicationDate |
2005-12-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2005274689-A1 |
| titleOfInvention |
Printed wiring board, production process thereof and semiconductor device |
| abstract |
A printed wiring board comprising an insulating film, a wiring pattern formed on at least one surface of the insulating film, a metal plating layer on the wiring pattern, and a resin protective layer provided on the wiring pattern with the metal plating layer in between so as to expose terminal portions of the wiring pattern plated with the metal, wherein the metal plating layer on the wiring pattern has a surface roughness (Rz) of 1.1 μm or above. A semiconductor device includes the printed wiring board and an electronic component mounted thereon. In production of the printed wiring board, the wiring pattern is surface roughened prior to forming the metal plating layer such that the metal plating layer formed thereon will have a surface roughness (Rz) of 1.1 μm or above. The surface roughening treatment of the wiring pattern reduces problems such as foaming in the resin protective layer by thermal shock even when the metal plating layer is made of a low-activity metal such as gold. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011100687-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007107930-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8791370-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9105631-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8872040-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10020280-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I484614-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-102969299-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2013048358-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7807932-B2 |
| priorityDate |
2004-05-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |