http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005221620-A1

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_dd467702ade456525b7168b3e349ae53
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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30608
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-302
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-306
filingDate 2004-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b2cc0ee1ebe19afe5bb0a99ec24615f6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_23a65f40545b98bf01a896841eb8455a
publicationDate 2005-10-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2005221620-A1
titleOfInvention Process for etching a substrate
abstract The invention relates to a process for etching at least one substrate, in particular at least one silicon wafer for the fabrication of DRAM memory chips. The process comprising at least one substrate, for a first etching step, is arranged for a predetermined time in a first vessel containing a first etchant, then at least one substrate, for a first rinsing step, is arranged for a predetermined time in a second vessel containing a first rinsing agent, the first rinsing agent containing at least one wetting agent, and then at least one substrate, for a second etching step, is arranged for a predetermined time in a third vessel containing a second etchant.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2012252212-A1
priorityDate 2004-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 27.