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filingDate 2003-11-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_79799e6646c6a1697e369a8555496f76
publicationDate 2005-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2005106842-A1
titleOfInvention Method of forming a polysilicon layer comprising microcrystalline grains
abstract A method of forming a flash memory cell includes providing a substrate, forming an oxide layer over the substrate, forming a polysilicon floating gate over the oxide layer including providing a bottom seed layer having microcrystalline polysilicon, providing an upper amorphous silicon layer over the bottom seed layer, and annealing the upper amorphous silicon layer, providing an inter-poly dielectric layer over the floating gate, and forming a polysilicon control gate over the inter-poly dielectric layer.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7914619-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8895435-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010112792-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005189597-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8101478-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8133801-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010001280-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9583559-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2012193796-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8647969-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102012100869-B4
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Total number of triples: 40.