| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-143
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2203-1105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2203-107
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-388 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-421
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-486 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-14 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-498
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-42 |
| filingDate |
2003-09-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_54a9b0c76fcdaafb6ec81d7d883f2395
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_297e2ecaae53a1fa44cf660929988cf2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d8a6e9a606c8a8250ee1346e42d3618e |
| publicationDate |
2005-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2005067679-A1 |
| titleOfInvention |
Stitched micro-via to enhance adhesion and mechanical strength |
| abstract |
A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material. The integrated circuit packaging substrate also includes a via for interconnecting the first layer of conductive material and the second layer of conductive material having a base that includes an interfacial adhesion material to stitch the base of the via to a layer of circuitry. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7692301-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-102097334-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007117339-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7737025-B2 |
| priorityDate |
2003-09-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |