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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-3185
filingDate 2004-10-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6f4e871eeae52884cdf332af28581239
publicationDate 2005-03-03-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2005050414-A1
titleOfInvention Hierarchical access of test access ports in embedded core integrated circuits
abstract An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8566656-B2
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2008046631-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10078115-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7003707-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011148445-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7650542-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2001037480-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006156099-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7219283-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9671464-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011239062-A1
priorityDate 1998-02-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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