http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005009324-A1

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filingDate 2004-04-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d924ab8eaef43ee237c8e3030e803535
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publicationDate 2005-01-13-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2005009324-A1
titleOfInvention Trench etch process for low-k dielectrics
abstract The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018138077-A1
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7932181-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011266695-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7541281-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8119523-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006094221-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006094219-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007293043-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9666479-B2
priorityDate 2001-10-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 45.