| abstract |
Aspects of the invention may include a data transition circuit ( 600 ) for formatting data from a first data bus having a first bus width to be compatible with a second data bus having a second bus width. The data transition circuit ( 600 ) may include a selector ( 606 ) adapted to receive an m-bit input clocked into the selector at a first clock rate from the first data bus. The selector may also be adapted to produce an n-bit output. The selector may include a select signal that may be configured to connect at least a portion of the m-bit input of the selector to the n-bit output of the selector. A first-in-first-out (FIFO) buffer ( 608 ) may be coupled to the selector ( 606 ) and adapted to buffer the n-bit output of the selector ( 606 ). The selector ( 606 ) may be configured so that the n-bit output of selector ( 606 ) may be clocked into the FIFO buffer at a second clock rate. Additionally, the n-bit output of selector ( 606 ) may be clocked out of the FIFO buffer ( 608 ) at a second clock rate onto the second data bus. |