| abstract |
A storage system controller ( 302 ) includes a plurality of media controllers ( 301 ), a local microprocessor ( 306 ), and a host interface logic ( 310 ), operably coupled by a multi-drop parallel bus. The multi-drop parallel bus includes a control bus ( 324 ), a payload data bus ( 320 ), a real-time ready-status (data ready) signaling bus ( 322 ) and a general microprocessor bus ( 330 ). Each media controller has a storage media ( 311 ) operably coupled thereto. Each media controller includes a parameter storage ( 404 ), a media interface circuit ( 406 ), a control data state machine ( 408 ), a command sequencer state machine ( 410 ), a media-side multi-mode transfer state machine ( 412 ), a dual-port memory ( 402 ), a memory controller ( 420 ), and a host-side transfer state machine ( 430 ). The host interface logic and the media controllers are implemented in one or more Field Programmable Gate Arrays. The storage system architecture allows the microprocessor to simultaneously broadcast a command to the media controllers, which have a capability to substantially simultaneously begin exchanging data with the storage media in response to the command. The storage system has provision for Redundant Array of Independent Disks, method 0, operation. |