http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2003184351-A1

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filingDate 2003-03-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4a8bda0909e83921eec627484f0b1cd4
publicationDate 2003-10-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2003184351-A1
titleOfInvention Timing signal occurrence circuit
abstract Object of the present invention is to provide a timing signal occurrence circuit capable of precisely adjusting timing, without complicating a circuit. n A timing signal occurrence circuit according to the present invention has a tristate buffer connected to a delay clock line, a tristate buffer connected to an operand bus, a calculator connected to an input terminal of each of the tristate buffers, a pulse generating circuit for generating an one shot pulse based on a delay clock on the delay clock line, and a calculator for fetching operands on the operand bus and carrying out calculation using the fetched operands. Either of a plurality of tristate buffers is arbitrarily selected to adjust delay time of the delay clock. Because of this, it is possible to generate a one shot pulse with optimum timing for carrying out calculation by the calculator.
priorityDate 1999-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 36.