Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3ad65c3edf9da24953f09acb2b71550 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-104 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-91 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-05 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0214 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-377 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4085 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-03 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-86 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4074 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-147 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-033 |
classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-314 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-02 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C5-14 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4074 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-408 |
filingDate |
2003-02-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5090417f7e5b9938c4d1a80c1bb888db http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_471f00ebad3a7a122ee4c5ef69f40017 |
publicationDate |
2003-08-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-2003151071-A1 |
titleOfInvention |
DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same |
abstract |
A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrate. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7253047-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7291880-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005285201-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005285163-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2003020106-A1 |
priorityDate |
1998-08-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |