| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5647
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5643
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5642
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5641
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-565
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5621 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5628
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5621
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5642
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3427
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3459
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3454
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-56 |
| filingDate |
2003-02-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d56fa6783409c53379de0bc3a3d0ce55
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_82680f9e5fe94d823f56b0fb00d04c06 |
| publicationDate |
2003-08-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2003147282-A1 |
| titleOfInvention |
Nonvolatile memory device and refreshing method |
| abstract |
At the data programming, plural data bit is transformed by a data transforming logic circuit into multi-value data according to the combination of bits, and the transformed data are sequentially transferred to a latch circuit connected to bit lines of a memory array. A program pulse is generated according to the latched data and is applied to a memory element at a state corresponding to the multi-value data. During data reading, the states of the memory elements are read out by changing the read voltage to intermediate values of individual threshold values and latched in a register. The original data may be restored by a data inverse transforming logic circuit based on the multi-value data stored in the register. |
| priorityDate |
1995-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |