http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2003147275-A1

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-412
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-412
filingDate 2003-01-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4aa4ad5454a12893f647c9d7b54e2ee7
publicationDate 2003-08-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2003147275-A1
titleOfInvention Schottky diode static random access memory (DSRAM) device, a method for making same, and CFET based DTL
abstract A high speed, low power Static Random Access Memory (SRAM) Array, which includes a 4T cell with two integrated Schottky Barrier Diodes (SBD) is disclosed. In a preferred embodiment, the cell bulk area and speed advantage is 30%, and ac power saving is 75% compared with the 6T CFET cell. The physical construct of the 4T cell saves capacitance in all critical nodes intra or inter cell wise, eliminates pass transistors, reduces the well noises. Typical embodiment uses a 0.15-um-rule based layout, and 1.5V supports operation at 5 ns cycles. SBD are used extensively with CFET to form a CMOS version of the Diode Transistor Logic circuitry. Generic control functions can be implemented including NAND gates, level shifting, decoding, voltage generator, ESD and latch-up protection, leakage control, and dynamic VT setting while in operation. Product applications include DRAM, SRAM, PLD, DRAM, CAM, Flash, Computing, Networking, and Communication devices as standalone system component or embedded into any ASIC.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I760477-B
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9153304-B2
priorityDate 2001-06-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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