http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2003119301-A1

Outgoing Links

Predicate Object
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76801
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76837
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
filingDate 2001-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0ff509db07a371039af87b3b78ae9488
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4136554a44124757a0287b584eac90fb
publicationDate 2003-06-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2003119301-A1
titleOfInvention Method of fabricating an IMD layer to improve global planarization in subsequent CMP
abstract A method of fabricating an IMD layer is provided on a semiconductor substrate, on which at least two adjacent metal wiring lines separated by a gap are patterned. A first dielectric layer, preferably of silicon oxide, is formed on the metal wiring lines to partially fill the gap below the level of the top of the metal wiring lines using high density plasma chemical vapor deposition (HDPCVD). Then, a second dielectric layer, preferably of silicon oxide, is formed on the first dielectric layer to completely fill the gap to a predetermined thickness using PECVD. Thus, the first dielectric layer and the second dielectric layer between the two adjacent metal wiring lines serve as the IMD layer.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11508653-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006038293-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006246719-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007099010-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I757074-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006265868-A1
priorityDate 2001-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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Total number of triples: 24.