http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2003085467-A1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C25D7-123 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C25D3-38 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2885 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-288 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D3-38 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D7-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate | 2002-12-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e0f961f0a1fe69cf0408aa90c6bc7456 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_646e9de2589c69360087b857e15aaba3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c6da63ba83d25c56e69d56dd6162d065 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7b3242163a845860575bafdeee500298 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5f39d3959f177d932eb740ff7f7edab7 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_13029005aeec852fbaeaa834522d8b69 |
| publicationDate | 2003-05-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-2003085467-A1 |
| titleOfInvention | Plating method, plating solution, semiconductor device and process for producing the same |
| abstract | A plating method comprising using a plating solution containing an additive satisfying the following conditions: n 0.005× h 2 /W<D/κ<0.5×h 2 /w, n and n 0.01≦Θ≦0.7 n wherein D is a diffusion coefficient of the additive; κ is a surface reaction rate of adsorption or consumption of the additive; h is a height of a trench or hole; w is the width of the trench or the radius of the hole; and Θ is a ratio of (plating film growth rate in the presence of additive)/(plating film growth rate in the absence of additive), is suitable for forming the plating metal in the trench or hole having the width of 1 μm or less (trench) or the radius of 1 μm or less (hole) without generating voids, and particularly suitable for producing semiconductor devices, which can have a multilayer structure of copper wiring layers formed on a semiconductor substrate by using the plating conditions, wherein at least one layer of copper wiring layers is plated in different conditions from the rest of the copper wiring layers. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1617469-A3 |
| priorityDate | 1999-09-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 49.