| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5621
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-565
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5647
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5643
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5642
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5641 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5628
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5621
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5642
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3454
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3459
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3427
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-56 |
| filingDate |
2002-08-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_82680f9e5fe94d823f56b0fb00d04c06 |
| publicationDate |
2003-02-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2003035317-A1 |
| titleOfInvention |
Nonvolatile memory device and refreshing method |
| abstract |
At the data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is applied to a memory element of a selected state correspondingly to the multi-value data. At the data reading operation, the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi-value data, so that the original data may be restored by a data inverse transforming logic circuit on the basis of the multi-value data stored in the register. As a result, the peripheral circuit scale of the memory array can be suppressed to a relatively small size, and programming operation performed in a short time can be realized. |
| priorityDate |
1995-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |