| abstract |
The present invention is a method that can simultaneously and reliably optimize the clock propagation delay time and clock skew of the entire semiconductor integrated circuit. For this reason, in the present invention, a clock-supplying element and a plurality of clock-receiving elements are first disposed. Then, a wiring path is determined while adjusting both a wired state and a buffer-inserting position from the clock-receiving elements toward the clock-supplying element. Such a method according to the present invention is employed, for example, in the layout of a semiconductor integrated circuit such as an integrated circuit, a large-scale integration, etc. Particularly, it is employed in the automatic layout of a clock distributing circuit. |