| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9fc0a00eab3a757e8324b1e887d7ba97 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02381
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02488
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02505
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02521
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02546 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0605
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8258 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8258 |
| filingDate |
2001-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c158a6d6ac3842e213780e20f9d16cbd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_99ab350a6c92b627e88b7f8e3757bed9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4091f1c4cb7707970bd6815f2a861815 |
| publicationDate |
2002-12-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2002181826-A1 |
| titleOfInvention |
Structure and method for fabricating a high-speed interface in semiconductor structures |
| abstract |
High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates by forming a compliant substrate for growing the monocrystalline layers. One way to achieve compliancy includes first growing on a silicon wafer an accommodating buffer layer that is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. In this way, high speed devices can be fabricated along with integral silicon-based circuitry to provide an efficient, low-cost semiconductor structure. Moreover, I/O pins and their associated problems can be eliminated. |
| priorityDate |
2001-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |