| abstract |
A plurality of chip-use element formation areas and scribe line areas for dividing the plurality of chip-use element formation areas are formed on a wafer. On each scribe line area, a interconnection 1 is formed so as to surround each chip-use element formation area, and is extended to the vicinity of an end edge P of a wafer. With this arrangement, it is possible to provide a semiconductor device and a manufacturing method thereof, which can reduce a difference in the depositing rate of plating between the center portion and the peripheral portion of the wafer. |