| abstract |
An imaging device comprises a semiconductor substrate including an array of pixel cells. Each pixel cell comprising an individually addressable pixel circuit for accumulating charge resulting from radiation incident on a pixel detector. The pixel circuit and the pixel detector can either be implemented on a single substrate, or on two substrates bonded together. The charge storage device can be a transistor, for example one of a pair of FET transistors connected as a cascade amplification stage. An imaging plane can be made up of one imaging device or a plurality of imaging devices tiled to form a mosaic. The imaging devices may be configured as a slot for certain applications, the slit or slot being scanned over the imaging plane. Control electronics can include addressing logic for addressing individual pixel circuits for reading accumulated charge from the pixel circuits. Imaging optimization can be achieved by determining maximum and minimum charge values for pixels for display, assigning extreme grey scale or colour values to the maximum and minimum charge values and allocating grey scale or colour values to an individual pixel according to a sliding scale between the extreme values. Scattered radiation can be detected and discarded by comparing the detected pixel value to a threshold value related to a minimum detected charge value expected for directly incident radiation and discarding detected pixel values less than said threshold value. |