http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2002059486-A1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3243 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3237 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3203 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-32 |
| filingDate | 2001-11-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6f14f42696c128330015e6a4a4dbd5ab http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ce06daede93dd9c1fb7f57999500c224 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_555ff07159a94b58f60e1fb7592835ec http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e5cf0a54c114df876fbf20c4ceaa14d0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_492db496ef4c561b6cc4c5be270851ec |
| publicationDate | 2002-05-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-2002059486-A1 |
| titleOfInvention | Shared component clock protection for multicore DSP device |
| abstract | A digital signal processing chip having a multiple processor cores with corresponding processor subsystems, a shared component, and a clock tree, is disclosed herein. A clock tree distributes clock signals to the processor cores and the shared component. The clock tree can be configured to disable one or more of the processor cores and the shared component by blocking the corresponding clock signal. This may advantageously conserve power. However, the clock tree is configured to preserve the clock signal to the shared component as long as at least one of the processor cores has not disabled the shared component. That is, to block the clock signal to the shared component, each of the processor cores must disable the shared component. The shared component may, for example, be a shared program memory or an arbiter for an external input/output port. The clock tree may include a register and a series of clock gates. Each of the clock gates blocks the clock signal when a gate signal is de-asserted. The gate signals are generated from enablement bits in the register. The clock signal for the shared component is gated by a clock gate that blocks the clock signal only if each of the processor cores have disabled their enablement bit for the shared component. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11509450-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101038501-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007271130-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10419198-B2 |
| priorityDate | 2000-11-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 34.