| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_58054227722081749d7e8e121924a5c8 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-0411
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5643
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5642 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3459
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1072
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1068
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1048
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5628
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M13-2906
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5642 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-04 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M13-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M13-29
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-10 |
| filingDate |
2021-06-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2023-01-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0823c10a6eef9e0111e2443c88a36424
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_792dcd818d4c0bf7470c0c16b43e8edd |
| publicationDate |
2023-01-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11557339-B2 |
| titleOfInvention |
Semiconductor storage device and memory system |
| abstract |
According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data. |
| priorityDate |
2016-09-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |