| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_82a9e22a923eca64a02a97f0dfb493ed |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0669
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-167
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-167
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 |
| filingDate |
2020-07-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2023-01-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2a08b039ac7703ff28ab078d004b75a1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_46d4e46120d1dbe6e95ba0d71da1091f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d26235f30ab9a0cb790a7e946398b91f |
| publicationDate |
2023-01-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11545555-B2 |
| titleOfInvention |
Gate-all-around (GAA) transistors with shallow source/drain regions and methods of fabricating the same |
| abstract |
Gate-all-around (GAA) transistors with shallow source/drain regions and methods of fabricating the same provide a GAA transistor that includes one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire, nanosheet, or nanoslab semiconductors, are surrounded along a longitudinal axis by gate material. At a first end of the channel is a source region and at an opposite end of the channel is a drain region. To reduce parasitic capacitance between a bottom gate and the source and drain regions, a filler material is provided adjacent the bottom gate, and the source and drain regions are grown on top of the filler material. In this fashion, the bottom gate does not abut the source region or the drain region, reducing geometries which would contribute to parasitic capacitance. |
| priorityDate |
2020-07-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |