| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06541
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14634
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-585
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1469 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-58
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-146 |
| filingDate |
2019-12-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4e79fb54ab461ad7c54a6f6e4edb5063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5ac71c1e98ae9c2807dbd2f4a33fbbc0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3e0d9795c1dd7fbcb00bf54e3fa46923
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d1fbc87a5b4493645e9ccd11b76867b3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4e3180744381d56477d3ae806175b9da |
| publicationDate |
2022-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11532661-B2 |
| titleOfInvention |
3DIC seal ring structure and methods of forming same |
| abstract |
A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate. The semiconductor device further includes a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate. The semiconductor device further includes a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, and a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip. |
| priorityDate |
2014-01-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |