| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_12d24c0a12c3ecdb6d9a47d623d96e76 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-0603 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5385
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-072
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-33
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49844
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5386
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3735
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49811 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-498
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-528 |
| filingDate |
2020-10-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-12-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_23005559a728a1e8ddb511f0b25e13c3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aba481d3c5c2af0a82e53692cc776127
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8f101b5cd6d319edd6d6d22588b2445e |
| publicationDate |
2022-12-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11521925-B2 |
| titleOfInvention |
Semiconductor module |
| abstract |
A semiconductor module, including a board that has first and second conductive plates located side by side on a first insulating plate, a first external connection terminal located on the first conductive plate, first and second semiconductor chips respectively disposed on the first and second conductive plates, and a printed-circuit board including a second insulating plate and first and second wiring boards located on a first principal plane of the second insulating plate. The first wiring board electrically connects an upper surface electrode of the first semiconductor chip and a relay area on the second conductive plate. The second wiring board is electrically connected to an upper surface electrode of the second semiconductor chip. The semiconductor module further includes a second external connection terminal electrically connected to an end portion of the second wiring board and formed on the second principal plane of the second insulating plate. |
| priorityDate |
2019-10-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |