| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_099413ae0cf5a2b6398b5151766cd260 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3266
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0286
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2320-043 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3266
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3674
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3688
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3677
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3696 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36 |
| filingDate |
2020-03-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-12-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d9eba8b38d8f9af7eae05fc39cd5a4fb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a89f5f523d5735eff46aa65a9b95e1e8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a4f13bf4d97dc2ebc1c7a43a46e0a7ad
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_35f0e68f79452e1c63f30a57a8bda622
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_31ec440eb39f9562f7f6ef79a8eb6d08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_921239c5d0af7a463fbc60f19230bdd9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_85d9f1df5f613c65663f9030d3bb8278 |
| publicationDate |
2022-12-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11521570-B2 |
| titleOfInvention |
Gate driver and display device including the same |
| abstract |
A gate driver for a display device includes: a clock signal line to transfer a clock signal; and a plurality of stages to sequentially output a gate signal based upon the clock signal in response to a carry signal. The plurality of stages include a plurality of thin film transistors, and at least one of the plurality of thin film transistors includes a thin film transistor including an oxide semiconductor. The at least one thin film transistor includes a first gate electrode and a second gate electrode disposed in different layers, the oxide semiconductor is disposed between the first gate electrode and the second gate electrode, and the first gate electrode and the second gate electrode are connected to receive a common voltage signal. |
| priorityDate |
2019-06-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |