| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_af4cc10d515454e59278de7445531247 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7824
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7812 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5228
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76243
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76251
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76254
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2007
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-84 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 |
| filingDate |
2019-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_49a997ef7ef87dba3b87955a74c626d8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_eb9aa27cc501813c7d3701b605b35afb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1e97bb6070536230e789b05c1c803206
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1039e3fe7257c42e926d800be9899dc6 |
| publicationDate |
2022-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11508612-B2 |
| titleOfInvention |
Semiconductor on insulator structure comprising a buried high resistivity layer |
| abstract |
A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL). |
| priorityDate |
2016-02-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |