| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5223
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0733
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53295
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L49-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522 |
| filingDate |
2019-06-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-11-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_06c65f3e16be8e38b9563d0c488aeee6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c9b02a5ec90bdec045590230631e5ee8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1d1679c2be0234fe91f5ac12115037cf |
| publicationDate |
2022-11-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11495658-B2 |
| titleOfInvention |
Hybrid high and low stress oxide embedded capacitor dielectric |
| abstract |
An electronic device, e.g. integrated circuit, has top and bottom metal plates located over a substrate, the bottom plate located between the top plate and the substrate. A high-stress silicon dioxide layer is located between the bottom plate and the substrate. At least one low-stress silicon dioxide layer is located between the top plate and the bottom plate. |
| priorityDate |
2018-06-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |