| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a21085e60a0630db07bbbb95b26616c1 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02532
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0262
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02579
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02576 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02532
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1012
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7436
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1027
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10802
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10844
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-01
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66393
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0262
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-39
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8221 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-74
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10 |
| filingDate |
2021-04-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-09-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1f5b4fb9ad2cd4ee267c49726efc5c2b |
| publicationDate |
2022-09-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11444085-B2 |
| titleOfInvention |
Multi-layer thyristor random access memory with silicon-germanium bases |
| abstract |
A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described. |
| priorityDate |
2018-06-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |