| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76837
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31111
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5329 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-532 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 |
| filingDate |
2020-01-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-08-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_eab04d970549ef9458baa933a5c4693c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_21c2350ac620e700b913b7415f66fecb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9109b68b55594387713c374f294c46cb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_337c73316e986c8c90bc56901d0a2631 |
| publicationDate |
2022-08-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11430864-B2 |
| titleOfInvention |
VFET device with controllable top spacer |
| abstract |
Techniques for controlling top spacer thickness in VFETs are provided. In one aspect, a method of forming a VFET device includes: depositing a dielectric hardmask layer and a fin hardmask(s) on a wafer; patterning the dielectric hardmask layer and the wafer to form a fin(s) and a dielectric cap on the fin(s); forming a bottom source/drain at a base of the fin(s); forming bottom spacers on the bottom source/drain; forming a gate stack alongside the fin(s); burying the fin(s) in a dielectric fill material; selectively removing the fin hardmask(s); recessing the gate stack to form a cavity in the dielectric fill material; depositing a spacer material into the cavity; recessing the spacer material to form top spacers; removing the dielectric cap; and forming a top source/drain at a top of the fin(s). A VFET device is also provided. |
| priorityDate |
2018-07-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |