| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K2017-6875
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K2017-0806 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K17-102
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K17-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02H3-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K17-0822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-012 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K17-687 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-012
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K17-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K17-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H02H3-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K17-082 |
| filingDate |
2021-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-06-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_722d719d2f13652404fd189f9c0abbb5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1b62e35ff3b1df93fd715649ad0124fe
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4a3a1f269c2869f18fe7c0a61a2363d6 |
| publicationDate |
2022-06-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11356087-B2 |
| titleOfInvention |
Method and circuitry for controlling a depletion-mode transistor |
| abstract |
In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node. |
| priorityDate |
2013-11-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |