| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02546
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02543
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-158
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7785 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-15
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-778 |
| filingDate |
2017-12-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-05-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d758b195b4feaba683c252d6ee6c4046
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8e980122b0937ebb79125f5638c94801
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5e2175c9219bbc793c8dde3f525f64c3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_74b593d93367e812acae50a26a4ae96c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_67fa3d7ac4541b1d51ad6f612f66e2cf
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_510bed3755984b20f0eb57be81dde6b4 |
| publicationDate |
2022-05-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11335796-B2 |
| titleOfInvention |
Source to channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs) |
| abstract |
Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate, and a channel area above the substrate and including a first III-V material. A source area may be above the substrate and including a second III-V material. An interface between the channel area and the source area may include the first III-V material. The source area may include a barrier layer of a third III-V material above the substrate. A current is to flow between the source area and the channel area through the barrier layer. Other embodiments may be described and/or claimed. |
| priorityDate |
2017-12-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |