patent/US-11315894-B2

http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11315894-B2

Outgoing Links

Predicate	Object
assignee	http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37
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classificationCPCInventive	http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-6835 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3135 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-80 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-495 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-561 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-50
classificationIPCInventive	http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-065 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-683
filingDate	2020-09-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate	2022-04-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor	http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_98b7d6eb7c2a664909e8afb2da965c6f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ef6b609a395ee0ec7e9bb208a03107fa http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7b925db99d8ad0ef9df503325f70697b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_51d13cf5822fef791b31cd4d4b94f32c
publicationDate	2022-04-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber	US-11315894-B2
titleOfInvention	Semiconductor stack and method for manufacturing the same
abstract	A semiconductor stack and a method for manufacturing the same are disclosed. The semiconductor stack includes a lower chip, an upper chip disposed over the lower chip, an upper lateral-side passivation layer surrounding side surfaces of the upper chip, and a plurality of bonding pads and a bonding passivation layer disposed between the upper chip and the lower chip.
priorityDate	2020-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type	http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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isDiscussedBy	http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID5461123 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419559541

Total number of triples: 53.