| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f52ff1051e70cfb44f47eb80bf2ca79b |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-65 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-55
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-23
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-501 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-501
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L49-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-23 |
| filingDate |
2020-12-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-04-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7881e5b50415f2013ed1f80e271300ed
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0d365cce3f6007c0390ac480268d5e11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5292d41fabdb5407708c5cd75f9bceda
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8e313dd2ca9be444b88dc1e4a2526b46
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e914bd8a43482d50788d8726fbf4a98f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_32edfa8afad2be358d7eb217e2e80f14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_caf7b286a64cc911a1ef3cd46eb1b6e1 |
| publicationDate |
2022-04-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11296708-B2 |
| titleOfInvention |
Low power ferroelectric based majority logic gate adder |
| abstract |
An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed. |
| priorityDate |
2019-12-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |