http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11294419-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03C3-0966 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-135 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-017 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03C3-0991 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-0231 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-1565 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-07 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-0315 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-08 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03C3-09 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-156 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-07 |
| filingDate | 2021-01-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2022-04-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d5a098a0d29a6689b5dc3b525d50a526 |
| publicationDate | 2022-04-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-11294419-B2 |
| titleOfInvention | Clock duty cycle adjustment and calibration circuit and method of operating same |
| abstract | A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to a first phase clock signal, a second phase clock signal and a set of control signals, and adjust the second duty cycle responsive to the set of control signals or a phase difference between the first phase clock signal and the second phase clock signal. The calibration circuit is configured to perform a duty cycle calibration of a second duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration. |
| priorityDate | 2018-08-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 44.